1. Field of the Invention
The present invention relates to a memory that is used for data storage in an electronic apparatus such as a personal computer (PC), and, more particularly, to a memory device having an interface function, a control method for the memory device, a control program for the memory device, a memory card, a circuit board and electronic equipment.
2. Description of the Related Art
A PC is provided with such JEDEC (Joint Electron Device Engineering Council) standard memories as a SDRAM (Synchronous Dynamic Random Access Memory) and DDR-SDRAM (Double Data Rate-SDRAM).
With respect to such a memory, Japanese Patent Application Laid-Open Publication No. 2004-110785 (ABSTRACT, FIG. 1, etc.) discloses a memory controller that includes a plurality of programmable timing registers that can be programmed to store timing data fit to a memory device. Japanese Patent Application Laid-Open Publication No. (H)06-208515 (ABSTRACT, FIG. 1, etc.) discloses a memory card that incorporates therein a microprocessor chip and a nonvolatile memory chip that are connected to each other via an internal card bus, the microprocessor chip containing key data, usage data and program command data. Japanese Patent Application Laid-Open Publication No. (H)09-6722 (ABSTRACT, FIG. 2, etc.) discloses a computer system having an input/output processor provided as a built-in processor connected to a local memory. Japanese Patent Application Laid-Open Publication No. 2005-196486 (paragraph 0029, FIG. 6, etc.) discloses a memory having an SPI driver and a memory means that are arranged inside the memory. Published Japanese Translations of PCT International Publication for Patent Applications No. (H)09-507325 (ABSTRACT, FIG. 1, etc.) discloses a data processing system including a CPU that is linked to a data memory via a single-direction readout bus, a single-direction writing-in bus and an address bus. Japanese Patent Application Laid-Open Publication No. 2002-63791 (ABSTRACT, FIG. 1, etc.) discloses a memory system in which a memory controller is connected to a memory via a writing-in data transfer bus and a readout data transfer bus that are separately disposed. Japanese Patent Application Laid-Open Publication No. (H)11-328975 (ABSTRACT, FIG. 2, etc.) discloses a random-access memory configured in such a way that data transfer to random-access memories is controlled in response to first translation of a period signal and data transfer from an array of random-access memories is controlled in response to second translation of the period signal. Japanese Patent Application Laid-Open Publication No. (H)07-169271 (paragraph 0038, FIG. 1, etc.) discloses a semiconductor memory device that includes a DRAM, and a CDRAM having a DRAM control and cache/refresh control unit. Japanese Patent Application Laid-Open Publication No. (H)08-124380 (paragraph 0020, FIG. 2, etc.) discloses a synchronous DRAM that has a memory array and a control unit and that allows setting of a mode register only when the data contents of a data bus is equal to operation status check data. Japanese Patent Application Laid-Open Publication No. (H)09-259582 (paragraph 0028, FIG. 1, etc.) discloses a mode register control circuit provided as an SDRAM and so on.
As shown in FIG. 1, a conventional memory module 2 includes a circuit board that carries a plurality of memory chips 41, 42, . . . and 4N and an SPD (Serial Presence Detect) memory unit 6. The memory chips 41, 42, . . . and 4N are connected to a memory access bus 8, and the SPD memory unit 6 is connected to an SPD access bus 10. In this memory module 2, the specifications and functions of the memory chips 41, 42, . . . and 4N, such as types and timing parameters of the memory chips, are stored on the SPD memory unit 6. As a result, consistency of the memory module 2 with a setting environment depends on control data stored on the SPD memory unit 6. The SPD memory unit 6 stores memory-related control data, which includes memory-related various parameters such as CAS (Column Array Strobe) latency, burst length, and additive latency. These control data are the data for setting different values depending on a chip set and a CPU (Central Processing Unit) that control memories. The SPD memory unit 6 is comprised of such a nonvolatile memory as EEPROM (Electrically Erasable Programmable Read-only Memory) Keeping control parameters necessary for memories in a component separated from the memories requires handling and control corresponding to the separate parameter storage, leading to an increase in various costs including product cost and writing-in cost.
Although the memory module 2 has a number of memory chips 41, 42, . . . and 4N, the specification of each of the memory chips 41, 42, . . . and 4N is regulated by the SPD memory unit 6. This makes impossible separate use of each of the memory chips 41, 42, . . . and 4N as a memory chip having a different specification. In other words, such a memory module 2 lacks flexibility in practical use.
The above patent documents suggest or disclose nothing about the above problems, and disclose nothing about a solution to the problems, either.